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标题: IEC 62142-2005 Verilog 寄存器传送级合成 [打印本页]

作者: sigh007 时间: 2012-3-21 20:43:13 标题: IEC 62142-2005 Verilog 寄存器传送级合成

【英文标准名称】: Verilog? register transfer level synthesis 【原文标准名称】: Verilog 寄存器传送级合成【标准号】: IEC 62142-2005 【标准状态】: 作废【国别】: 国际【发布日期】: 2005-06 【实施或试行日期】: 【发布单位】: 国际电工委员会(IX-IEC)【起草单位】: IEC/TC 93【标准类型】: ()【标准水平】: ()【中文主题词】: 计算机系统布局;数据类型;程序结构;程序交换;程序设计指令;通路控制;程序设计技术;计算机硬件;数据处理;程序描述;语义学;数据格式;程序;程序模型;句法;数据传送;VERILOG;工具;接口(数据处理);程序设计语言;程序展示;验证;定义【英文主题词】: Access controls;Computer hardware;Computer systems configuration;Data formats;Data processing;Data transfer;Data types;Definitions;Interfaces (data processing)

rogram architecture

rogram description

rogram interchange

rogram module

rogram presentation

rogrammes

rogramming instructions

rogramming languages

rogramming techniques;Semantics;Syntax;Tools;Verification;Verilog【摘要】: This standard defines a set of modeling rules for writing Verilog HDL descriptions for synthesis. Adher-ence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard defines how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.Use of this standard will enhance the portability of Verilog-HDL-based designs across synthesis tools con-forming to this standard. In addition, it will minimize the potential for functional mismatch that may occur between the RTL model and the synthesized netlist.【中国标准分类号】: L63【国际标准分类号】: 35_060【页数】: 116P.;A4【正文语种】: 英语

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