标题: IEEE Std 1800-2017 IEEE Standard for SystemVerilog [打印本页] 作者: yy480 时间: 2018-10-11 09:10:24 标题: IEEE Std 1800-2017 IEEE Standard for SystemVerilog
[attach]181480[/attach][attach]181481[/attach]
IEEE Std 1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages. 作者: admin 时间: 2018-10-14 10:05:17